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rev. c a ad5300 * information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. 2.7 v to 5.5 v, 140 a, rail-to-rail output 8-bit dac in a sot-23 functional block diagram power-on reset dac register input control logic ad5300 v dd gnd v out sync sclk din 8-bit dac ref (+) ref (? output buffer power-down control logic resistor network features single 8-bit dac 6-lead sot-23 and 8-lead msop packages micropower operation: 140 a @ 5 v power-down to 200 na @ 5 v, 50 na @ 3 v 2.7 v to 5.5 v power supply guaranteed monotonic by design reference derived from power supply power-on reset to 0 v 3 power-down functions low power serial interface with schmitt-triggered inputs on-chip output buffer amplifier, rail-to-rail operation sync interrupt facility applications portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators general description the ad5300 is a single, 8-bit buffered voltage output dac that operates from a single 2.7 v to 5.5 v supply, consuming 115 a at 3 v. its on-chip precision output amplifier allows rail-to-rail output swing to be achieved. the ad5300 uses a versatile 3-wire serial interface that operates at clock rates up to 30 mhz and is compatible with standard spi , qspi, microwire , and dsp interface standards. the reference for ad5300 is derived from the power supply inputs and thus gives the widest dynamic output range. the part incorporates a power-on reset circuit that ensures that the dac output powers up to 0 v and remains there until a valid write takes place to the device. the part contains a power-down feature that reduces the current consumption of the device to 200 na at 5 v and provides software selectable output loads while in power- down mode. the part is put into power-down mode over the serial interface. the low power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment. the power consumption is 0.7 mw at 5 v, reducing to 1 w in power-down mode. the ad5300 is one of a family of pin compatible dacs. the ad5310 is the 10-bit version and the ad5320 is the 12-bit version. the ad5300/ad5310/ad5320 are available in 6-lead sot-23 packages and 8-lead msop packages. product highlights 1. available in 6-lead sot-23 and 8-lead msop packages. 2. low power, single-supply operation. this part operates from a single 2.7 v to 5.5 v supply and typically consumes 0.35 mw at 3 v and 0.7 mw at 5 v, making it ideal for battery- powered applications. 3. the on-chip output buffer amplifier allows the output of the dac to swing rail-to-rail with a slew rate of 1 v/ s. 4. reference derived from the power supply. 5. high speed serial interface with clock speeds up to 30 mhz. designed for very low power consumption. the interface powers up only during a write cycle. 6. power-down capability. when powered down, the dac typically consumes 50 na at 3 v and 200 na at 5 v. * patent pending; protected by u.s. patent no. 5684481.
e2e rev. c ad5300especifications (v dd = 2.7 v to 5.5 v; r l = 2 k to gnd; c l = 500 pf to gnd; all specifications t min to t max , unless otherwise noted.) b version 1 parameter min typ max unit conditions/comments static performance 2 resolution 8 bits relative accuracy 1 lsb see figure 2. differential nonlinearity 0.25 lsb guaranteed monotonic by design. see figure 3. zero-code error +0.5 +3.5 lsb all zeros loaded to dac register. see figure 6. full-scale error e0.5 e3.5 lsb all ones loaded to dac register. see figure 6. gain error 1.25 % of fsr zero-code error drift e20 v/ c gain temperature coefficient e5 ppm of fsr/ c output characteristics 3 output voltage range 0 v dd v output voltage settling time 4 6 s 1/4 scale to 3/4 scale change (40 hex to c0 hex). r l = 2 k ; 0 pf < c l < 500 pf. see figure 16. slew rate 1 v/ s capacitive load stability 470 pf r l = . 1000 pf r l = 2 k . digital-to-analog glitch impulse 20 nv-s 1 lsb change around major carry. see figure 19. digital feedthrough 0.5 nv-s dc output impedance 1 short-circuit current 50 ma v dd = 5 v. 20 ma v dd = 3 v. power-up time 2.5 s coming out of power-down mode. v dd = 5 v. 5 s coming out of power-down mode. v dd = 3 v. logic inputs 3 input current 1 a v inl , input low voltage 0.8 v v dd = 5 v. v inl , input low voltage 0.6 v v dd = 3 v. v inh , input high voltage 2.4 v v dd = 5 v. v inh , input high voltage 2.1 v v dd = 3 v. pin capacitance 3 pf power requirements v dd 2.7 5.5 v i dd (normal mode) dac active and excluding load current. v dd = 4.5 v to 5.5 v 140 250 av ih = v dd and v il = gnd. v dd = 2.7 v to 3.6 v 115 200 av ih = v dd and v il = gnd. i dd (all power-down modes) v dd = 4.5 v to 5.5 v 0.2 1 av ih = v dd and v il = gnd. v dd = 2.7 v to 3.6 v 0.05 1 av ih = v dd and v il = gnd. power efficiency i out /i dd 93 % i load = 2 ma. v dd = 5 v. notes 1 temperature range as follows: b version: e40 c to +105 c. 2 linearity calculated using a reduced code range of 4 to 251. output unloaded. 3 guaranteed by design and characterization, not production tested. specifications subject to change without notice.
ad5300 e3e rev. c timing characteristics 1, 2 limit at t min , t max parameter v dd = 2.7 v to 3.6 v v dd = 3.6 v to 5.5 v unit conditions/comments t 1 3 50 33 ns min sclk cycle time t 2 13 13 ns min sclk high time t 3 22.5 13 ns min sclk low time t 4 13 13 ns min sync scs s sc sync sync ns s sc s sc sync n s n sns c n n n c c s c c c s c s c c s c c c s c c s cn s s s nn ssnsc n cs c c c c c c c c c c c c c c c c c c ns ss
ad5300 e4e rev. c pin configurations top view (not to scale) 6 5 4 1 2 3 v out gnd v dd sync sclk din ad5300 top view (not to scale) 8 7 6 5 1 2 3 4 nc ad5300 sync v out gnd v dd sclk din nc nc = no connect sot-23 msop pin function descriptions sot-23 msop pin no. pin no. mnemonic function 14v out analog output voltage from dac. the output amplifier has rail-to-rail operation. 28 gnd ground reference point for all circuitry on the part. 31v dd power supply input. these parts can be operated from 2.5 v to 5.5 v, and v dd should be decoupled to gnd. 47 din serial data input. this device has a 16-bit shift register. data is clocked into the register on the falling edge of the serial clock input. 56 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data can be transferred at rates up to 30 mhz. 65 sync c sync c sync sync c nc nc nc
ad5300 e5e rev. c terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot can be seen in figure 2. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code plot can be seen in figure 3. zero-code error zero-code error is a measure of the output error when zero code (00 hex) is loaded to the dac register. ideally, the output should be 0 v. the zero-code error is always positive in the ad5300 because the output of the dac cannot go below 0 v. this is due to a combination of the offset errors in the dac and output amplifier. zero-code error is expressed in lsbs. a plot of zero-code error vs. temperature can be seen in figure 6. full-scale error full-scale error is a measure of the output error when full- scale code (ff hex) is loaded to the dac register. ideally, the output should be v dd e 1 lsb. full-scale error is expressed in lsbs. a plot of full-scale error vs. temperature can be seen in figure 6. gain error this is a measure of the span error of the dac. it is the devia- tion in slope of the dac transfer characteristic from ideal expressed as a percent of the full-scale range. total unadjusted error total unadjusted error (tue) is a measure of the output error taking into account all the various errors. a typical tue vs. code plot can be seen in figure 4. zero-code error drift this is a measure of the change in zero-code error with a change in temperature. it is expressed in v/ c. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/ c. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv-secs and is measured when the digital input code is chan ged by 1 lsb at the major carry transition (7f hex to 80 hex). see figure 19. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac but is measured when the dac output is not updated. it is specified in nv-secs and is measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s, and vice versa.
code inl error e lsbs 1.0 0.5 e1.0 050 250 100 150 200 0 e0.5 inl @ 3v inl @ 5v t a = 25 c figure 2. typical inl plot temperature e c error e lsbs 1.0 0.5 e1.0 e40 0 120 40 80 0 e0.5 max inl min inl max dnl min dnl v dd = 5v figure 5. inl error and dnl error vs. temperature i source/sink e ma v out e v 3 2 0 0 515 10 1 dac loaded with ff hex t a = 25 c dac loaded with 00 hex figure 8. source and sink current capability with v dd = 3 v code dnl error e lsbs 0.5 0.4 e0.5 050 250 100 150 200 e0.1 e0.2 e0.3 e0.4 0.3 0.1 0.2 0 t a = 25 c dnl @ 5v dnl @ 3v figure 3. typical dnl plot temperature e c 3 2 e3 e40 120 04080 0 e1 v dd = 5v error e lsbs e2 1 zs error fs error figure 6. zero-scale error and full-scale error vs. temperature i source/sink e ma v out e v 5 4 0 0 515 10 3 2 1 dac loaded with 00 hex t a = 25 c dac loaded with ff hex figure 9. source and sink current capability with v dd = 5 v code tue e lsbs 1.0 0.5 e1.0 0 50 250 100 150 200 0 e0.5 t a = 25 c tue @ 5v tue @ 3v figure 4. typical total unadjusted error plot 2500 2000 500 50 1500 1000 0 frequency 70 90 110 130 150 170 190 60 80 100 120 140 160 180 v dd = 3v v dd = 5v i dd e a figure 7. i dd histogram with v dd = 3 v and v dd = 5 v code i dd e a 500 400 0 0 50 250 100 150 200 300 200 100 v dd = 3v v dd = 5v figure 10. supply current vs. code ad5300etypical performance characteristics e6e rev. c
ad5300 e7e rev. c temperature e c i dd e a 0 e40 80 040 300 100 50 120 v dd = 5v 150 200 250 figure 11. supply current vs. temperature v logic e v 800 600 0 01 5 234 400 200 t a = 25 c v dd = 5v v dd = 3v i dd e a figure 14. supply current vs. logic input voltage 2k load to v dd ch1 1v, ch 2 1v, time base = 20 s/div v dd v out ch1 ch2 figure 17. power-on reset to 0 v v dd e v i dd e a 300 250 0 2.7 3.2 5.2 3.7 4.2 4.7 200 150 100 50 figure 12. supply current vs. supply voltage v out clk ch1 1v, ch 2 5v, time base = 1 s/div ch1 ch 2 v dd = 5v full-scale code change 00 hex e ff hex t a = 25 c output loaded with 2k and 200pf to gnd figure 15. full-scale settling time ch1 1v, ch 2 5v, time base = 5 s/div ch2 ch1 clk v out v dd = 5v figure 18. exiting power-down (7f hex loaded) v dd e v 1.0 0.9 0 2.7 3.2 5.2 3.7 4.2 4.7 0.4 0.3 0.2 0.1 0.8 0.6 0.7 0.5 threeestate condition e40 c +25 c +105 c i dd e a figure 13. power-down current vs. supply voltage v out clk v dd = 5v half-scale code change 40 hex e c0 hex t a = 25 c output loaded with 2k and 200pf to gnd ch1 1v, ch2 5v, time base = 1 s/div ch 1 ch 2 figure 16. half-scale settling time v out e v 500ns/div 2.54 2.46 2.50 2.48 2.52 loaded with 2k and 200pf to gnd code change: 80 hex to 7f hex figure 19. digital-to-analog glitch impulse
ad5300 e8e rev. c general description d/a section the ad5300 dac is fabricated on a cmos process. the archi- tecture consists of a string dac followed by an output buffer amplifier. since there is no reference input pin, the power supply (v dd ) acts as the reference. figure 20 shows a block diagram of the dac architecture. v dd v out gnd resistor string ref (+) ref (e) output amplifier dac register figure 20. dac architecture since the input coding to the dac is straight binary, the ideal output voltage is given by v out = v dd d 256 where d = decimal equivalent of the binary code that is loaded to the dac register; d can range from 0 to 255. resistor string the resistor string section is shown in figure 21. it is simply a string of resistors, each of value r. the code loaded to the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaran- teed monotonic. r r to output amplifier r r r figure 21. resistor string output amplifier the output buffer amplifier is capable of generating rail-to-rail voltages on its output, which gives an output range of 0 v to v dd . it is capable of driving a load of 2 k in parallel with 1000 pf to gnd. the source and sink capabilities of the output amplifier can be seen in figures 8 and 9. the slew rate is 1 v/ s with a half-scale settling time of 4 s with the output loaded. serial interface the ad5300 has a 3-wire serial interface ( sync sc nssc ss sync n sc s c sync sync s sync n n sync s c csc c s s nn n n s ns s c
ad5300 e9e rev. c power-down circuitry resistor network v out resistor string dac amplifier figure 24. output stage during power-down the bias generator, the output amplifier, the resistor string, and other associated linear circuitry are all shut down when the power-down mode is activated. however, the contents of the dac register are unaffected when in power-down. the time to exit power-down is typically 2.5 s for v dd = 5 v and 5 s for v dd = 3 v (see figure 18). microprocessor interfacing ad5300 to adsp-2101/adsp-2103 interface figure 25 shows a serial interface between the ad5300 and the adsp-2101/adsp-2103. the adsp-2101/adsp-2103 should be set up to operate in the sport transmit alternate framing mode. the adsp-2101/adsp-2103 sport is programmed through the sport control register and should be configured as follows: internal clock operation, active low framing, 16-bit word length. transmission is initiated by writing a word to the tx register after the sport has been enabled. adsp-2101/ adsp-2103 * dt * additional pins omitted for clarity sync din sclk ad5300 * tfs sclk figure 25. ad5300 to adsp-2101/adsp-2103 interface db15 db0 sclk sync din db15 db0 valid write sequence, output updates on the 16 th falling edge invalid write sequence: sync high before 16 th falling edge figure 23. sync sync sync scc sync c c c c n n n s n n
ad5300 e10e rev. c * additional pins omitted for clarity sync din ad5300 * sclk microwire * sk so cs figure 28. ad5300 to microwire interface applications using ref19x as a power supply for ad5300 b ecause the supply current required by the ad5300 is extremely low, an alternative option is to use a ref19x voltage reference (ref195 for 5 v or ref193 for 3 v) to supply the required voltage to the part?see figure 29. this is especially useful if your power supply is quite noisy or if the system supply voltages are at some value other than 5 v or 3 v (e.g., 15 v). the ref19x will output a steady supply voltage for the ad5300. if the low dropout ref195 is used, the current it needs to supply to the ad5300 is 140 a. this is with no load on the output of the dac. when the dac output is loaded, the ref195 also needs to supply the current to the load. the total current required (with a 5 k load on the dac output) is 140 a + (5 v/5 k ) = 1.14 ma t he load regulation of the ref195 is typically 2 ppm/ma, which results in an error of 2.3 ppm (11.5 v) for the 1.14 ma current drawn from it. this corresponds to a 0.0006 lsb error. ad5300 3-wire serial interface sync sclk din 15v 5v 140 a v out = 0v to 5v ref195 figure 29. ref195 as power supply to ad5300 bipolar operation using the ad5300 the ad5300 has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in figure 30. the circuit in figure 30 will give an output voltage range of 5 v. rail-to-rail operation at the amplifier output is achievable using an ad820 or an op295 as the output amplifier. the output voltage for any input code can be calculated as vv drr r v r r odd dd = +
256 12 1 2 1 e where d represents the input code in decimal (0 to 255). with v dd = 5 v, r1 = r2 = 10 k , v o = 10 d 256 e5 v t his is an output voltage range of 5 v with 00 hex corresponding to a e5 v output and ff hex corresponding to a 5 v output. ad5300 to 68hc11/68l11 interface figure 26 shows a serial interface between the ad5300 and the 68hc11/68l11 microcontroller. sck of the 68hc11/68l11 drives the sclk of the ad5300, while the mosi output drives the serial data line of the dac. the sync c c cc c sync cc s scsc s c cc nnscy sync n sc c sc s c c c c csc sync c c c s s c nnscy sync n sc c c c cs s
ad5300 e11e rev. c 0.1 f v dd 10k power 10 f v dd sync sclk data ad5300 5v regulator v dd 10k v dd 10k v out din sync sclk gnd figure 32. ad5300 with an opto-isolated interface power supply bypassing and grounding when accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. the printed circuit board containing the ad5300 should have separate analog and digital sections, each having its own area of the board. if the ad5300 is in a system where other devices require an agnd to dgnd connection, the connec- t ion should be made at one point only. this ground point should be as close as possible to the ad5300. th e power supply to the ad5300 should be bypassed with 10 f and 0.1 f capacitors. the capacitors should be physi- cally as close as possible to the device with the 0.1 f capacitor ideally right up against the device. the 10 f capacitors are the t antalum bead type. it is important that the 0.1 f capacitor has low effective series resistance (esr) and effective series induc tance (esi), e.g., common ceramic types of capacitors. this 0.1 f capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line itself should have as large a trace as pos- sible to provide a low impedance path and reduce glitch effects on the supply line. clocks and other fast switching digital signals s hould be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. the best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. however, this is not always possible with a 2-layer board. r2 = 10k +5v e5v ad820/ op295 3-wire serial interface +5v ad5300 10 f 0.1 f v dd v out r1 = 10k 5v figure 30. bipolar operation with the ad5300 two 8-bit ad5300s together make one 15-bit dac by using the configuration in figure 31, it can be seen that one 15-bit dac can be made with two 8-bit ad5300s. because of the low supply current the ad5300 requires, the output of one dac may be directed into the supply pin of the second dac. the first dac has no problem sourcing the required 140 a of current for the second dac. since the ad5300 works on any supply voltage between 2.5 v and 5.5 v, the output of the first dac can be anywhere above 2.5 v. for a v dd of 5 v, this allows the first dac to use half of its output range (2.5 v to 5 v), which gives 7-bit resolution on the output voltage. this output then becomes the supply and reference for the second dac. the second dac has 8-bit reso- lution on the output range, which gives an overall resolution for the system of 15 bits. a level-shifter is required to ensure that the logic input voltages do not exceed the supply voltage of the part. the microcontroller outputs 5 v signals, which need to be level shifted down to 2.5 v in the case of the second dac having a supply of only 2.5 v. 5v micro- controller v out = 2.5v to 5v level shifter v out = 0v to 5v 15-bit resolution sync sclk din v dd ad5300 ad5300 v dd sync sclk din figure 31. 15-bit dac using two ad5300s using ad5300 with an opto-isolated interface in process-control applications in industrial environments, it is often necessary to use an opto-isolated interface to protect and isolate the controlling circuitry from any hazardous common- mode voltages that may occur in the area where the dac is functioning. opto-isolators provide isolation in excess of 3 kv. because the ad5300 uses a 3-wire serial logic interface, it requires only three opto-isolators to provide the required isola- tion (see figure 32). the power supply to the part also needs to be isolated. this is done by using a transformer. on the dac side of the transformer, a 5 v regulator provides the 5 v supply required for the ad5300.
ad5300 e12e rev. c c00471e0e11/03(c) 6-lead small outline transistor package [sot-23] (rt-6) dimensions shown in millimeters 1 3 4 5 2 6 2.90 bsc pin 1 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 0.22 0.08 10 4 0 0.50 0.30 0.15 max 1.30 1.15 0.90 seating plane 1.45 max 0.60 0.45 0.30 compliant to jedec standards mo-178ab 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters 0.80 0.60 0.40 8 0 85 4 1 4.90 bsc pin 1 0.65 bsc 3.00 bsc seating plane 0.15 0.00 0.38 0.22 1.10 max 3.00 bsc coplanarity 0.10 0.23 0.08 compliant to jedec standards mo-187aa revision history location page 11/03?data sheet changed from rev. b to rev. c. changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 updated pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 outline dimensions

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